Method and apparatus for testing bumped die

ABSTRACT

An apparatus for testing unpackaged semiconductor dice having raised ball contact locations is disclosed. The apparatus uses a temporary interconnect wafer that is adapted to establish an electrical connection with the raised ball contact locations on the die without damage to the ball contact locations. The interconnect is fabricated on a substrate, such as silicon, where contact members are formed in a pattern that matches the size and spacing of the ball contact locations on the die to be tested. The contact members on the interconnect wafer are formed as either pits, troughs, or spike contacts. The spike contacts penetrate through the oxide layer formed on the raised ball contact locations. Conductive traces are provided in both rows and columns and are terminated on the inner edges of the walls of the pits formed in the substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 10/218,379,filed Aug. 13, 2002, pending, which is a continuation of applicationSer. No. 09/923,688, filed Aug. 6, 2001, now U.S. Pat. No. 6,486,552,issued Nov. 26, 2002, which is a continuation of application Ser. No.09/521,592, filed Mar. 9, 2000, now U.S. Pat. No. 6,303,993, issued Oct.16, 2001, which is a divisional of application Ser. No. 08/994,004,filed Dec. 18, 1997, now U.S. Pat. No. 6,140,827, issued Oct. 31, 2000.

BACKGROUND OF THE INVENTION

The present invention relates generally to semiconductor manufacturingand, more particularly, to methods for testing semiconductor dice havingraised or bumped bond pads. More particularly still, the presentinvention relates to fabricating and using a testing grid suitable fortesting solder balls used for bumped bond pads on an unpackagedsemiconductor die.

Semiconductor dice are being fabricated with raised bond pads and areknown as bumped semiconductor die. A bumped semiconductor die includesbond pads along with bumped solderable material such as a lead-tinalloy. These typically are manufactured from solder balls made of alead-tin alloy. Bumped dies are often used for flip-chip bonding wherethe die is mounted face down on the substrate, such as a printed circuitboard, and then the die is attached to the substrate by welding orsoldering. Typically, the bumps are formed as balls of materials thatare circular in a cross-sectional plane parallel to the face of the die.The bumps typically have a diameter of from 50 micrometers (μm) to 100μm. The sides of the bumps typically bow or curve outwardly from a flattop surface. The flat top surface forms the actual region of contactwith a mating electrode on the printed circuit board or other substrate.In testing the attached solder bumps, a temporary electrical connectionmust be made between the contact locations or bond pads on the die andthe external test circuitry associated with the testing apparatus. Thebond pads provide a connection point for testing an integrated circuiton the die. Likewise, the integrity of each bump must be tested as well.

In making this temporary electrical connection, it is desirable toeffect a connection that causes as little damage as possible to thebumped die. If the temporary connection to the bumped bond pad damagesthe pad, the entire die may be ruined. This is difficult to accomplishbecause the connection must also produce a low resistance or ohmiccontact with the bumped bond pad. A bond pad, with or without a bump,typically has a metal oxide layer formed over it that must be penetratedto make the ohmic contact.

Some prior art contact structures, such as probe cards, scrape the bondpads and wipe away the oxide layer. This causes excess layer damage tothe bond pads. Other interconnect structures, such as probe tips, maypierce the oxide layer and metal bond pad and leave a deep gouge. Stillother interconnect structures, such as micro bumps, cannot even piercethe oxide layer, preventing the formation of an ohmic contact.

In the past, following testing of a bump pad die, it has been necessaryto reflow the bumps, which are typically damaged by the procedure. Thisis an additional process step that adds to the expense and complexity ofthe testing process. Furthermore, it requires heating the tested diethat can adversely affect the integrated circuitry formed on the die.

Other bond pad integrity testing systems have been developed in theprior art. Typically, these testing systems use optical imaging todetermine the integrity of the weld connection on the bumped sites. Onetype of system is a profiling system that uses interferometry withrobotic wafer handling to automate the testing step. The testing stepdevelops a profile for measuring solder bump heights. Unfortunately,although the interferometry system does not damage the device in anyway, the time required for analyzing each bump location can take fromtwo to four minutes. This type of throughput is unacceptable when a highspeed system is necessary.

Accordingly, what is needed is a method and system for testing solderbumps in bond pad locations that does not damage the bond pads whileimproving throughput.

BRIEF SUMMARY OF THE INVENTION

According to the present invention, a method and apparatus for testingunpackaged semiconductor dice having raised contact locations aredisclosed. The apparatus uses a temporary interconnect wafer that isadapted to establish an electrical connection with the raised ballcontact locations on the die without damage to the ball contacts. Theinterconnect wafer is fabricated on a substrate, such as silicon, wherecontact members are formed in a pattern that matches the size andspacing of the contact locations on the die to be tested. The contactmembers on the interconnect wafer are formed as either pits, troughs, orspike contacts. The spike contacts penetrate through the oxide layerformed on the raised ball contact location. Conductive traces areprovided in both rows and columns and are terminated on the inner edgesof the walls of the pits formed in the substrate. This arrangementallows a system to measure the continuity across the bump pad or ballcontact locations of the integrated circuit die in order to establishthat each ball contact location is properly attached. This also allowsthe system to test for the presence and quality of the bump or ballcontact locations on the particular die being tested.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional diagram of a pit formed in asubstrate wherein a solder ball is received;

FIG. 2 is a cross-sectional perspective schematic view of the pitaccording to FIG. 1;

FIG. 3 is a top plan view of an array of pits according to that of FIG.1 having a metal interconnect in a form of rows and columns;

FIG. 4 is an alternative embodiment of the pit of FIG. 1 wherein raisedsupports are provided along with sharp blades for penetrating the ball;

FIG. 5 is an alternative embodiment of the pit of FIG. 1 wherein raisedportions are provided for penetrating the solder balls;

FIG. 6 is an example of a solder ball being out of place and failing tomake adequate connection between adjacent metal bonds;

FIG. 7 is an example of when a ball that is too small has beenidentified;

FIG. 8 is a schematic cross-sectional view of a device under test wheremismatched balls are adjacent to one another; and,

FIG. 9 is a block diagram of a test apparatus using the bump plateaccording to FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a cross-sectional schematic view of a bump plate 10 fortesting the connect conductivity and quality of a solder ball on anunpackaged semiconductor die. Bump plate 10 is fabricated in asemiconductor substrate 12, such as, for example, silicon, galliumarsenide, or silicon on sapphire, to name a few.

A plurality of receiving pits 14 is formed in the surface of substrate12. Receiving pit 14 can be any desired polygonal or curved shape, butis preferred to be square with four sloped sidewalls 16. Each sidewall16 is at an angle of 54° from horizontal, conforming to the plane of thesurface of the silicon substrate that can be used in fabricating bumpplate 10. After pits or suitable features are etched (formed), thesurface of the plate is coated with a thin layer insulator of about200-300 Angstroms (such as Si Oxide) before the metal traces are formed.Electrical connection for testing for the presence of the solder ballson the die is provided by metal traces 18. Metal traces 18 are made froma suitable metal and extend across the surface of substrate 12 and downsidewalls 16 of receiving pit 14. A solder ball or bump 20 can then bepositioned within receiving pit 14 and contact all four sloped sidewalls16. Ball 20 is placed within receiving pit 14 when a die under test ismated with bump plate 10. Since a metal trace 18 is placed on eachsidewall 16 and extends across the surface of substrate 12 to anadjacent receiving pit 14, an applied electric current can flow throughmetal traces 18 provided the solder ball 20 contacts both sides ofsidewall 16 and metal trace 18 thereon.

A method that is adaptable for manufacturing bump plate 10 is describedin U.S. Pat. No. 5,592,736, “Fabricating An Interconnect For TestingUnpackaged Semiconductor Dice Having Raised Bond Pads,” commonlyassigned to the same assignee as the present invention, and hereinincorporated by reference for all purposes.

FIG. 2 depicts, in a cross-sectional perspective view, receiving pit 14prior to the addition of metal trace 18 of FIG. 1. Receiving pit 14 hasa substantially flat bottom surface that is non-conductive as well asfour adjacent sidewalls 16, again having the slope angle that naturallyslopes 54° in the surface plane of silicon substrate 12 as it is etched.The sloped sidewall 16 allows for a spherical ball 20 to seat withinreceiving pit 14 without damaging the bottom curvature of ball 20 whilestill contacting metal trace 18 that extends down the slope of sidewall16.

Bump plate 10 has a plurality of receiving pits 14 and is shown in theschematic diagram of FIG. 3. Bump plate 10 actually is an array ofreceiving pits 14 that is electrically connected in rows and columnsusing metal traces 18. Horizontal metal traces 18 run across the surfaceof substrate 12 and down the sloped sidewalls 16 of the receiving pits14. It is important that metal traces 18 do not connect with one anotherwithin receiving pits 14. As an electric current is placed across eachrow and down each column in a sequential manner, it becomes readilyapparent at each receiving pit 14 location whether a ball exists or theconnection is of such poor quality as to provide no conduction acrossthe row or down the column. From this information, a grid map of thedefects can be established that will allow repair of the missing or poorquality bumped locations at a subsequent repair stage.

Alternative embodiments to receiving pits 14 within the substrate 12 areshown in FIGS. 4 and 5. FIG. 4 illustrates a raised contact location 30for contacting the bottom surface of a solder ball 20. Each raisedcontact location 30 comprises a set of side bumps 32 that form a valley36. A plurality of sharpened projections 34 is formed within valley 36and is designed to pierce the oxide layer formed over ball 20 and can beattached to adjacent metal traces 18 for providing good ohmic contact toadjacent metal traces 18 with ball 20 for testing purposes. Contactlocation 30 can be in the shape of a polygon or circle and can becombined with receiving pits 14 of FIG. 3.

FIG. 5 is an alternative embodiment where each receiving pit 14 isreplaced with a post trough 40, which is formed by a plurality of posts42 to form a polygon, such as a square. Posts 42 are formed such that avalley 44 is formed in post trough 40. Metal traces are formed up anddown the sides of post 42, but not connecting one another in the samemanner as traces 18 in FIG. 3. Thus, when a ball 20 is placed in a posttrough 40, a good ohmic connection forms between opposite traces 18 forconducting a test current. Further, post trough 40 can be in the shapeof a polygon or circle and can be combined with receiving pits 14 ofFIG. 3 or contact locations 30 of FIG. 4.

Each of the embodiments of FIGS. 1-5 is capable of testing for varioustypes of solder ball conditions. The most significant is when a missingball occurs. This is simple to detect in that no current will floweither across the column or down the row when the test current isapplied. Other examples are also possible and are illustrated in FIGS.6, 7, and 8. FIG. 6 is an example of when a solder ball 20 is off centerand only contacts one or two sides of receiving pit 14, thus preventinga good current signal from passing either across the column or down therow. FIG. 7 is an example of a ball 20 too small to touch any sides inreceiving pit 14. In this condition, no current can pass and it isviewed as being that no solder ball is present. FIG. 8 depicts whereadjacent balls of different sizes are attached to die 50. A first ball20 has a first diameter and a second ball 52 has a second diameter,which is much smaller than the first diameter of ball 20. As is shown,ball 20 is an appropriate size and contacts well with the sides ofreceiving pit 14. By contrast, ball 52 is too small to even reachreceiving pit 14, so the current signal test shows it as not beingpresent at all. Of course, the reverse can be true in that ball 52 isactually the desired size of the balls while ball 20 is an aberrationand is much larger than desired. This would also be evident in that manyballs would be seen as not being present as the diameter of ball 20would prevent several adjacent balls from contacting in their respectivepits.

FIG. 9 depicts a test apparatus 54 that uses a bump plate 10. Apparatus54 comprises a signal processor, such as a computer system 56, thatattaches to a bump plate 10. Electrical signals or current are passed tobump plate 10 along the rows and columns of the metal traces 18 toestablish a test pattern. A device under test (DUT) 58 is pressed uponbump plate 10 to match the solder ball pattern to the identical patternfabricated on bump plate 10. Once contact is made, the test is begun andthe results are obtained more quickly compared to prior art testapparatus using optical or other mechanical means previously described.

The bump die wafer inspection apparatus of the present invention offersthe following advantages over the prior art. As the electronic worldmoves toward stencification miniaturization, better methods for testingthese technologies are needed and this solution provides an advancementover those previously available and, using semiconductor fabricationtechniques, a bump plate matching a desired solder ball pattern for aparticular die can be generated. The silicon or other similar substratesserve as a rigid medium, and as a result of this rigidity, they have afixed dimensional test capability for each bump/ball testing site. Thislimits its use with regard to the range of the dimensional tolerancesthat it can test. This is significant in that the bumps, or balls, orboth, require tight dimensional tolerances to pass such testing. Thesilicon micro-machining and photolithography processes allow much moreprecise geometry control than the printed circuit board (PCB) or filmtechnologies found in the prior art. Hence, a more definitivedistinction and grading is made for each ball shape and position.Additionally, the present apparatus provides a unique methodology forelectronically mapping the failing ball sites and then utilizing thismap to direct a repair or rework system to correct each failing site.These operations of testing, mapping, and subsequent repair can becombined in a highly automated in-line process, thus reducing thenecessary steps previously required in the prior art of removing the badboards and sending them to the rework section of the fabricationoperation.

Another advantage is since the semiconductor substrate can be planarizedto a uniform flatness compared to the PCB and other processingsolutions, less damage is caused to the good solder balls attached tothe DUT.

Thus the invention provides an improved method and system for testing adiscrete, unpackaged semiconductor die having raised bond pads. Althoughspecific materials have been described, it is understood that othermaterials can be utilized. Furthermore, although the method of theinvention has been described with reference to certain specificembodiments as will be apparent to those skilled in the art,modifications can be made without departing from the scope of theinvention as defined in the following claims.

1. A bump substrate for use during the testing of a semiconductor diehaving bond pads having a raised contact bumps thereon extending above asurface of said semiconductor die comprising: a bump substrate having aplurality of contact bump receiving sites formed therein, each of saidplurality of contact bump receiving sites having a plurality ofsidewalls and a bottom and having a plurality of conductive traceslocated on at least portions of said plurality of sidewalls thereof forcontacting a plurality of conductive traces on said bump substrate andfor contacting a corresponding contact bump of said contact bumps onsaid bond pads received at said plurality of contact bump receivingsites, a conductive trace of said plurality of conductive tracesextending along at least a portion of a sidewall of said plurality ofsidewalls of a contact receiving site and at least one other conductivetrace of said plurality of conductive traces extending along at least aportion of another sidewall of said plurality of sidewalls and a portionof said bottom of said contact receiving site, said plurality ofconductive traces forming a plurality of rows and a plurality of columnsinterconnecting each contact bump receiving site of said plurality ofcontact bump receiving sites to at least one adjacent contact bumpreceiving site of said plurality of contact bump receiving sites in anadjacent row of the plurality of rows and an adjacent column of theplurality of columns.
 2. The bump substrate according to claim 1,wherein said plurality of contact bump receiving sites comprise pitsfabricated in said bump substrate, each pit of said pits having opposingwalls wherein said plurality of conductive traces extend down saidopposing walls and are free from contact with each other.
 3. Anapparatus for testing for the presence of a ball in a plurality of ballslocated on the bond pads of a semiconductor die, comprising: a signalprocessor; and a bump wafer connected to said signal processor,comprising: a plurality of contact points formed in a semiconductorsubstrate having a pattern essentially corresponding to a pattern ofsaid plurality of balls on said semiconductor die; a plurality of metaltraces fabricated on said semiconductor substrate for at least one ofsaid contact points such that the placement of a contact ball on said atleast one contact point connects one of said first plurality of tracesto a second of said plurality of said traces.
 4. The apparatus accordingto claim 3, wherein said plurality of metal traces form an array of rowsand columns interconnecting at least one of said contact sites to atleast one adjacent contact site.
 5. The apparatus according to claim 3,wherein said contact sites comprise pits fabricated in saidsemiconductor substrate, each pit having opposing walls wherein some ofsaid plurality of metal traces extend down said opposing walls withoutcontacting one another.
 6. The apparatus according to claim 3, whereinsaid plurality of contact sites comprise: a plurality of risers, overwhich said such plurality of metal traces extend; and a plurality ofblades, situated between the said plurality of rises, to pierce an oxidelayer on said contact ball.
 7. The apparatus according to claim 3,wherein at least one contact location of said plurality of contactlocations comprises: a plurality of retaining posts, over each of whichextends one of said metal traces and in which a bump seat is formed forreceiving said contact bump.
 8. The apparatus according to claim 3,wherein said signal processor selectively applies and senses anelectrical current to each of said metal traces.
 9. A method of forminga bump plate from a semiconductor substrate for receiving a plurality ofcontact bumps on a semiconductor die, the method comprising: forming aplurality of contact bump receiving sites in said bump plate tocorrespond to a pattern established by a said plurality of contact bumpson said semiconductor die, at least one of said plurality of contactbump receiving sites having a plurality sidewalls; and forming aplurality of a conductive traces on said substrate and said sidewallsfor at least one contact site of said plurality of contact bumpreceiving sites to contact with a corresponding contact bump of saidplurality of contact bumps received at said contact site.
 10. The methodaccording to claim 9, wherein said forming a plurality of contact bumpreceiving sites in said bump plate comprises: applying a photo resistlayer on said substrate; exposing selected regions of said photo resistlayer; removing said exposed photo resist layer regions; and, etchingsaid removed regions to form said sidewalls in each of said plurality ofcontact receiving sites.
 11. The method according to claim 9, whereinsaid forming a plurality of a conductive traces on said substrate andsaid sidewalls comprises: applying a photo resist layer to saidsubstrate; exposing selected regions of said photo resist layer to formconductive trace patterns on said substrate; removing said exposed photoresist layer regions; and. forming a metal trace in said removed photoresist layer regions extending down each of said sidewalls of saidplurality of contact receiving sites.
 12. The method according to claim9, wherein said plurality of conductive traces form an array of rows andcolumns interconnecting each contact site to at least one adjacentcontact site.
 13. The method according to claim 9, wherein said contactsites comprise a plurality of pits fabricated in a semiconductorsubstrate having opposing walls having at least two of said plurality ofconductive traces extending down said opposing walls of a pit withoutcontacting one another.
 14. The method according to claim 9, whereinsaid forming a plurality of contact bump receiving sites in said bumpplate comprises: applying a photo resist layer on said substrate;exposing selected regions of said photo resist layer; removing saidexposed photo resist layer regions; forming a plurality of risers insaid removed regions; and, forming a plurality of blades, situatedbetween said plurality of risers.
 15. The method according to claim 9,wherein said forming a plurality of a conductive traces on saidsubstrate and said sidewalls comprises: applying a photo resist layer tosaid substrate; exposing selected regions of said photo resist layer toform conductive trace patterns on said substrate; removing said exposedphoto resist layer regions; and. forming a metal trace in said removedphoto resist layer regions extending over each of said plurality ofrisers.
 16. The method according to claim 9, wherein said forming aplurality of contact bump receiving sites in said bump plate comprises:applying a photo resist layer on said substrate; exposing selectedregions of said photo resist layer; removing said exposed photo resistlayer regions; and forming a plurality of retaining posts in saidremoved regions.
 17. The method according to claim 16, wherein saidforming a plurality of a conductive traces on said substrate and saidsidewalls for at least one contact site of said plurality of contactbump receiving sites comprises: applying a photo resist layer to saidsubstrate; exposing selected regions of said photo resist layer to formconductive trace patterns on said substrate; removing said exposed photoresist layer regions; and. forming a metal trace in said removed photoresist layer regions extending over each of said plurality of retainingposts.